Asynchronous Behaviors Meet Their Match with SystemVerilog Assertions

Most digital designs inherently possess asynchronous behaviors of some kind. While the SystemVerilog assertion (SVA) language offers some asynchronous controls like disable iff, writing concurrent assertions that accurately describe asynchronous behavior is not so straightforward. SVA properties require a clocking event, making them innately synchronous. When describing asynchronous behavior, the behavior of interest typically occurs after the asynchronous trigger appears. Unfortunately, SystemVerilog scheduling semantics make this rather difficult to check because the assertion input values are sampled before the trigger occurs. This often leads assertion writers to sampling using clocks, which may not guarantee matching and optimal checking in all cases. Alternatively, there are some simple approaches for describing asynchronous behavior using SVA that this paper explores. The SystemVerilog scheduling semantics are described along with the difficulties they pose for checking asynchronous behavior. Traditional approaches are considered such as synchronizing to a clock, but better asynchronous alternatives are suggested and practical examples provided. In addition, some practical solutions are offered for other asynchronous behaviors like asynchronous communication between clock domains or across bus interfaces. Lastly, this paper considers the various changes and additions to the recently published IEEE 1800-2009 standard, which may simplify checking asynchronous behavior.